1. Field of the Invention
This invention relates to a microprocessor suitable for performing graphics processes, and more particularly to graphics processing apparatus and method using the microprocessor and suitable for transferring graphics data between memories on separate buses.
2. Description of the Related Art
A conventional microprocessor system having two sets of buses, each set for address, data and control signals, is exemplified by Harvard Architecture. This conventional system is designed so as to avoid any contention between an instruction fetch and a data access by separating an instruction bus and a data bus.
Also, LSIs for graphics process are exemplified by a bit map control processor (BMCP) discussed in Toshiba Review 43th volume, 12th issue (1988), pages 932-935. This BMCP has an 8-bit data bus, as a system bus to which a CPU and a system momory are connected, and a 64-bit local memory data bus and a 24-bit address bus independently of the data bus; the address bus and local memory data bus access 8-plane local memories (image memories). Further, with an address latched, the BMCP can access the system memory.
In the Harvard Architecture, the instruction bus and the data bus are dedicated; the Harvard Architecture is totally silent about the concept of using two sets of buses in data access, such as in graphics transfer between a system memory and a frame memory which transfer is performed most frequently among various procedures of the graphics processing.
The BMCP may use two sets of buses in data access, but has only a single address bus; it is unclear from Toshiba Review that two memories can be simultaneously accessed.
Further, in executing a so-called read/modify/write instruction frequently used for graphics processing in which data in a memory address is read and processed and is then written back to the same address, conventional general microprocessors have the following problems.
First of all, in CISC (Complex Instruction Set Computer) type general processors, although a single instruction is capable of describing a read/modify/write operation with memory addresses designated for a source operand and a destination operand of the operation instruction, the length of instruction is necessarily long. Also, it is not clear if it is possible to make the execution without interposing a wait cycle between a read cycle and a write cycle.
In some of exclusive processors for graphics process, though a read/modify/write instruction can be executed in two successive memory cycles, its modifying function is limited.
In RISC (Reduced Instruction Set Computer) type processors, instructions are basically of a fixed length, and operands accessible to a memory are allowed to be designated only for a load instruction and a store instruction. Thus, execution of a read/modify/write operation requires three instructions, i.e. load, operation and store instructions, failing to execute the load and store instructions in two successive memory cycles.